\hypertarget{mt481c2m32b2tg_8h}{
\section{E:/Ausbildung/Semester3/AVR32\_\-Work1/Halos\_\-Development/src/hal/ports/avr32/ap7x/ap7000/mt481c2m32b2tg.h File Reference}
\label{mt481c2m32b2tg_8h}\index{E:/Ausbildung/Semester3/AVR32\_\-Work1/Halos\_\-Development/src/hal/ports/avr32/ap7x/ap7000/mt481c2m32b2tg.h@{E:/Ausbildung/Semester3/AVR32\_\-Work1/Halos\_\-Development/src/hal/ports/avr32/ap7x/ap7000/mt481c2m32b2tg.h}}
}
MT481C2M32B2TG SDRAM driver for AVR32 SDRAMC on EBI.  


\subsection*{Defines}
\begin{CompactItemize}
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_c30aecdb3c8680ab2eece9b5259d3479}{SDRAM\_\-COL\_\-BITS}~9
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_1e8b3213104955ec593852e69e2a7aad}{SDRAM\_\-ROW\_\-BITS}~13
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_896319a196dc59213dcc1cb08995e120}{SDRAM\_\-BANK\_\-BITS}~2
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_b7d533d7b18455c14d514c201a9c1c85}{SDRAM\_\-TR}~312
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_2e88af10dbd9bed2641d48ef00571954}{SDRAM\_\-CAS}~3
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_e9a0212f01930fe74d77aa67f986eb22}{SDRAM\_\-TWR}~2
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_79f005214551a79c0bde41ccd51a54c7}{SDRAM\_\-TRC}~7
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_151d0603d3b97dd3c099732a8c890adb}{SDRAM\_\-TRP}~2
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_d85453f4efb53f343c888878a5455b06}{SDRAM\_\-TRCD}~2
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_6970701fa2f373c8add41a374ff45493}{SDRAM\_\-TRAS}~5
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_5fd22f4aed855f302e992e9148d840c7}{SDRAM\_\-TXSR}~5
\item 
\hypertarget{mt481c2m32b2tg_8h_abac5a76a989b212e8621a99472aa471}{
\#define \hyperlink{mt481c2m32b2tg_8h_abac5a76a989b212e8621a99472aa471}{SDRAM\_\-INIT\_\-AUTO\_\-REFRESH\_\-COUNT}~8}
\label{mt481c2m32b2tg_8h_abac5a76a989b212e8621a99472aa471}

\begin{CompactList}\small\item\em The minimal number of AUTO REFRESH commands required during initialization for this SDRAM. \item\end{CompactList}\item 
\#define \hyperlink{mt481c2m32b2tg_8h_b2a22e57108a05109491956286291e5d}{SDRAM\_\-TRFC}~66
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_5c8c0d1f0afb668049fdadf420f7aee3}{SDRAM\_\-TMRD}~2
\item 
\#define \hyperlink{mt481c2m32b2tg_8h_fed2ca7a568253e359e3cbdd3b6b9b9b}{SDRAM\_\-STABLE\_\-CLOCK\_\-INIT\_\-DELAY}~100
\end{CompactItemize}


\subsection{Detailed Description}
MT481C2M32B2TG SDRAM driver for AVR32 SDRAMC on EBI. 

\begin{Desc}
\item[Note:]The values defined in this file are device-specific. See the device datasheet for further information.\end{Desc}
\begin{itemize}
\item Compiler: IAR EWAVR32 and GNU GCC for AVR32\item Supported devices: All AVR32 devices with an SDRAMC module can be used.\item AppNote:\end{itemize}


\begin{Desc}
\item[Author:]Atmel Corporation: \href{http://www.atmel.com}{\tt http://www.atmel.com} \par
 Support and FAQ: \href{http://support.atmel.no/}{\tt http://support.atmel.no/} \end{Desc}


\subsection{Define Documentation}
\hypertarget{mt481c2m32b2tg_8h_896319a196dc59213dcc1cb08995e120}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-BANK\_\-BITS@{SDRAM\_\-BANK\_\-BITS}}
\index{SDRAM\_\-BANK\_\-BITS@{SDRAM\_\-BANK\_\-BITS}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-BANK\_\-BITS}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-BANK\_\-BITS~2}}
\label{mt481c2m32b2tg_8h_896319a196dc59213dcc1cb08995e120}


The number of banks for this sdram. \hypertarget{mt481c2m32b2tg_8h_2e88af10dbd9bed2641d48ef00571954}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-CAS@{SDRAM\_\-CAS}}
\index{SDRAM\_\-CAS@{SDRAM\_\-CAS}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-CAS}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-CAS~3}}
\label{mt481c2m32b2tg_8h_2e88af10dbd9bed2641d48ef00571954}


The CAS latency for this sdram. \hypertarget{mt481c2m32b2tg_8h_c30aecdb3c8680ab2eece9b5259d3479}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-COL\_\-BITS@{SDRAM\_\-COL\_\-BITS}}
\index{SDRAM\_\-COL\_\-BITS@{SDRAM\_\-COL\_\-BITS}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-COL\_\-BITS}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-COL\_\-BITS~9}}
\label{mt481c2m32b2tg_8h_c30aecdb3c8680ab2eece9b5259d3479}


The number of columns for this sdram. \hypertarget{mt481c2m32b2tg_8h_1e8b3213104955ec593852e69e2a7aad}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-ROW\_\-BITS@{SDRAM\_\-ROW\_\-BITS}}
\index{SDRAM\_\-ROW\_\-BITS@{SDRAM\_\-ROW\_\-BITS}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-ROW\_\-BITS}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-ROW\_\-BITS~13}}
\label{mt481c2m32b2tg_8h_1e8b3213104955ec593852e69e2a7aad}


The number of rows for this sdram. \hypertarget{mt481c2m32b2tg_8h_fed2ca7a568253e359e3cbdd3b6b9b9b}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-STABLE\_\-CLOCK\_\-INIT\_\-DELAY@{SDRAM\_\-STABLE\_\-CLOCK\_\-INIT\_\-DELAY}}
\index{SDRAM\_\-STABLE\_\-CLOCK\_\-INIT\_\-DELAY@{SDRAM\_\-STABLE\_\-CLOCK\_\-INIT\_\-DELAY}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-STABLE\_\-CLOCK\_\-INIT\_\-DELAY}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-STABLE\_\-CLOCK\_\-INIT\_\-DELAY~100}}
\label{mt481c2m32b2tg_8h_fed2ca7a568253e359e3cbdd3b6b9b9b}


The minimal stable-clock initialization delay for this SDRAM. Unit: us. \hypertarget{mt481c2m32b2tg_8h_5c8c0d1f0afb668049fdadf420f7aee3}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TMRD@{SDRAM\_\-TMRD}}
\index{SDRAM\_\-TMRD@{SDRAM\_\-TMRD}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TMRD}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TMRD~2}}
\label{mt481c2m32b2tg_8h_5c8c0d1f0afb668049fdadf420f7aee3}


The minimal mode register delay time for this SDRAM. LOAD MODE REGISTER command to ACTIVE or REFRESH command delay. Unit: tCK (SDRAM cycle period). \hypertarget{mt481c2m32b2tg_8h_b7d533d7b18455c14d514c201a9c1c85}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TR@{SDRAM\_\-TR}}
\index{SDRAM\_\-TR@{SDRAM\_\-TR}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TR}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TR~312}}
\label{mt481c2m32b2tg_8h_b7d533d7b18455c14d514c201a9c1c85}


The refresh rate. NOTE: This is dependant on the clock frequency \hypertarget{mt481c2m32b2tg_8h_6970701fa2f373c8add41a374ff45493}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TRAS@{SDRAM\_\-TRAS}}
\index{SDRAM\_\-TRAS@{SDRAM\_\-TRAS}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TRAS}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TRAS~5}}
\label{mt481c2m32b2tg_8h_6970701fa2f373c8add41a374ff45493}


Minimal ACTIVE to PRECHARGE command. NOTE: This setting is dependant on the clock frequency. \hypertarget{mt481c2m32b2tg_8h_79f005214551a79c0bde41ccd51a54c7}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TRC@{SDRAM\_\-TRC}}
\index{SDRAM\_\-TRC@{SDRAM\_\-TRC}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TRC}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TRC~7}}
\label{mt481c2m32b2tg_8h_79f005214551a79c0bde41ccd51a54c7}


Minimal ACTIVE to ACTIVE command period. NOTE: This setting is dependant on the clock frequency \hypertarget{mt481c2m32b2tg_8h_d85453f4efb53f343c888878a5455b06}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TRCD@{SDRAM\_\-TRCD}}
\index{SDRAM\_\-TRCD@{SDRAM\_\-TRCD}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TRCD}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TRCD~2}}
\label{mt481c2m32b2tg_8h_d85453f4efb53f343c888878a5455b06}


Minimal ACTIVE to READ or WRITE delay. NOTE: This setting is dependant on the clock frequency \hypertarget{mt481c2m32b2tg_8h_b2a22e57108a05109491956286291e5d}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TRFC@{SDRAM\_\-TRFC}}
\index{SDRAM\_\-TRFC@{SDRAM\_\-TRFC}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TRFC}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TRFC~66}}
\label{mt481c2m32b2tg_8h_b2a22e57108a05109491956286291e5d}


The minimal refresh cycle time for this SDRAM. AUTO REFRESH command period. Unit: ns. \hypertarget{mt481c2m32b2tg_8h_151d0603d3b97dd3c099732a8c890adb}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TRP@{SDRAM\_\-TRP}}
\index{SDRAM\_\-TRP@{SDRAM\_\-TRP}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TRP}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TRP~2}}
\label{mt481c2m32b2tg_8h_151d0603d3b97dd3c099732a8c890adb}


Minimal PRECHARGE command period. NOTE: This setting is dependant on the clock frequency \hypertarget{mt481c2m32b2tg_8h_e9a0212f01930fe74d77aa67f986eb22}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TWR@{SDRAM\_\-TWR}}
\index{SDRAM\_\-TWR@{SDRAM\_\-TWR}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TWR}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TWR~2}}
\label{mt481c2m32b2tg_8h_e9a0212f01930fe74d77aa67f986eb22}


The write recovery time. NOTE: This setting is dependant on the clock frequency \hypertarget{mt481c2m32b2tg_8h_5fd22f4aed855f302e992e9148d840c7}{
\index{mt481c2m32b2tg.h@{mt481c2m32b2tg.h}!SDRAM\_\-TXSR@{SDRAM\_\-TXSR}}
\index{SDRAM\_\-TXSR@{SDRAM\_\-TXSR}!mt481c2m32b2tg.h@{mt481c2m32b2tg.h}}
\subsubsection[{SDRAM\_\-TXSR}]{\setlength{\rightskip}{0pt plus 5cm}\#define SDRAM\_\-TXSR~5}}
\label{mt481c2m32b2tg_8h_5fd22f4aed855f302e992e9148d840c7}


Minimal exit SELF REFREASH to ACTIVE command. NOTE: This setting is dependant on the clock frequency 